Assembly engineering faces a new and elusive problem that will only get worse unless systems houses institute sustained, disciplined measures to curtail it. Using incorrect or outdated programming algorithms and inadequate programming systems for newer, more advanced programmable ICs is at the crux of this problem. Because they give programming only cursory attention, many systems houses don't focus the necessary tools or resources on ensuring that device programming is properly performed. Incorrectly programmed devices can cause either immediate failures or latent problems that eventually lead to failures in the field. Making sure correct algorithms are used is becoming increasingly vital as chip makers change device specifications and associated algorithms more often than ever before. Failure to use updated algorithms causes programming errors and triggers a potential avalanche of costly problems in the factory and, subsequently, with customers.
Assembly engineers often blame chip makers for device failures. In most instances, however, the devices are fine but the algorithms have problems.
FIGURE 1: Typical programming algorithm. Data retention problems stem from using incorrect, unapproved algorithms.
More than 7,000 different programmable ICs are now available, including the newer, more complex PLDs. FPGAs and flash EEPROMs. Of these, devices (68%) receive four or more algorithm changes during their lifetimes. The percentage is even higher 85%-for such logic devices as PLDs, PALs and FPGAs.
Chip makers change specifications and algorithms for a variety of reasons. For example, they may want to increase programming yields, reduce costs, improve programming speeds and process yields, factor in new or additional device characteristics or increase long-term reliability.
FIGURE 2: The three algorithm elements that frequently change are Vee, program enable and program pulse.
A Vee usually starts at 5V. However, different process changes can increase that voltage to 5.25\/ or decrease it to 4.75V. Program enable, on the other hand, comprises function and programming/verifying modes. It can increase to a supervoltage, beyond the traditional 5V device supply voltage. The rate that the program enable increases should be factored into the manufacturer's specifications.
Program enable alterations also affect slew rates. For example, reducing a fast 25V/sec slew rate to 10 or 5V/usec. rate and not incorporating this revision can damage the device.
The third element, program pulse, involves voltage level and pulse width. It usually rests at 5V, but if changed by just 0.25V, it can alter a programming yield by 90 to 95%. The first revision of a complex PLD or FPGA, for instance, might require 10 pulses of 100 usec each. But improving the process would result in a pulse width of 10 pulses at 50 msec. each, thus dramatically reducing programming time.
Figure 3a shows an EPROM memory cell consisting of a single MOS transistor with a floating gate placed between the select gate and the transistor channel. Charges stored in the floating gate trigger the select gate voltage to turn the transistor on or off. The transistor in an unprogrammed cell turns on when the select gate voltage reaches Vee. This causes the cell to represent a logical "1" on the output.
During programming, the programmer system places voltages that are higher than normal operating voltages on the device's gate and drain. Some of the electrons flowing through the channel become sufficiently energized to penetrate the isolation oxide and remain in the floating gate even after the high voltage inputs are removed. Thus, a programmed cell registers a logical "O.'' Creating sufficient programming margin is important at this point. It involves storing more charges in the floating gate than necessary to turn the cell off. The excess charges allow the device to operatle under fluctuating supply voltages and to remain programmed over long periods of time.
If the margin is insufficient, data can be degraded or lost completely. This problem develops gradually after charges are trapped in the floating gate by an electron volt potential barrier in the isolating oxide, exposing them to thermal and UV energies. Exposure statistically excites the electrons beyond the barrier value so that they leave the cell (Figure 3b). Increasingly smaller numbers of stored charges then trigger a TTL select gate voltage to again turn on the cell transistor (logical "1").
This erases the cell, and programmed data is lost. Similarly, devices programmed with algorithms presenting little or no margin may read false data when environmental conditions cause supply voltage to fluctuate.
Chip edge rates are currently very fast. and systems designers using these devices must have an extremely clean and controlled programming environment. Otherwise, noise is introduced in the form of oscillations or simultaneous switching noise and ground bounce. In poorly structured programming systems. problems stem from impedance mismatching between a chip's pins and the programmer's pin driver (Figure 4). Impedances must be matched between pin drivers and chip pins and between chip pin outputs and the pin drivers readback circuitry. Pin driver impedances should be able to drive slew rates greater than 500V/usec and should not load down the high edge rates when a pin an an output.
The pin driver consists of multiple paths to a device's ground pin. Each path has to be impedance matched and finely tuned to parallel the device's pin, depending on the mode of the programmer.
FIGURE 3a: EPROM memory cell comprises a single MOS transistor with a floating gate between the select gate and the transistor channel.
The more sensitive an advanced programmable chip becomes relative to what it has to drive, the more critical those impedances are in the programmer itself. Impedance mismatching, therefore, leads to addressing errors and an assortment of other, sometimes undetected, glitches that result in programming failures.
FIGURE 3b: Stored charges are subjected to thermal and UV energies causing electrons to drift outside the cell and subsequently cause data loss.
FIGURE 4: For programming accuracy, impedances must be matched between pin drivers and chip pins and between chip pin outputs and the pin drivers' read back circuitry.
Next, all the systems were shipped back to the manufacturer with the customer incurring extremely high shipping costs. The manufacturer's engineering groups stopped work on other projects to troubleshoot this problem. They worked for about six weeks without resolving it. Finally, the manufacturer sent its chief engineer to the site in weather of -20deg F to see if he could find the cause of the problem.
A bad EPROM was subsequently found. and blame was immediately placed on the chip vendor. A lawsuit was threatened. Device inventories weie purged and restocked with another vendor's EPROM line.
Considerable administration and engineering time and resources went into these actions and, in the end, a good working relationship with a leading semiconductor company turned sour.
In reality, however, there was never actually a problem with the original EPROM. The traftic light manufacturer's mistake was using a lower-cost programmer that didn·t correctly program this EPROM.
The device was only marginally programmed, so the environmental conditions that occurred created the intermittent problem. However, the customer didn't care to understand the technical problems that had to be overcome. He only knew that the manufacturer was unable to produce a reliable system. As a result. the manufacturer lost the customer's business.
In this particular instance a savings of approximately $300 on a cheaper programmer resulted in the loss of reputation and major market share to the tune of millions of dollars.
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